首页   按字顺浏览 期刊浏览 卷期浏览 Transistor storage and logic circuits for binary data processing
Transistor storage and logic circuits for binary data processing

 

作者: R.Herman,  

 

期刊: Proceedings of the IEE - Part B: Electronic and Communication Engineering  (IET Available online 1959)
卷期: Volume 106, issue 16S  

页码: 663-674

 

年代: 1959

 

DOI:10.1049/pi-b-2.1959.0128

 

出版商: IEE

 

数据来源: IET

 

摘要:

The paper describes new types of transistor storage circuits for binary data processing. The active state is denned by the generation of a pulse waveform across the output windings of a transformer which is provided with a multiplicity of output windings, and the timing of the output signal is controlled by a clock waveform coupled to each circuit. This permits the design of logic circuits in which the output voltages generated by different storage circuits are combined additively or subtractively, by series connection of a group of output windings. The inclusion of a diode in each series-connected group allows parallel connection of several groups. In this way logic circuits corresponding to complex logical functions may be constructed in which the only components are diodes. Transistors and resistors may, however, also be included, giving added flexibility in design if required. Any of these logic circuits may be made to control the state of an associated storage circuit by direct connection of the output terminal of the logic circuit to the input terminal of the storage circuit.The storage circuits described are of two types, namely delayed and undelayed. A design is given for a parallel adder in which undelayed storage circuits are used for the ‘carry’ register and in which the addition process is completed in a single clock cycle. In an experimental circuit using type OC44 transistors and operating at a clock frequency of 500kc/s, correct operation is obtained for the addition of numbers up to six binary digits, giving a 7-digit sum. It should be possible to perform parallel operations on much larger numbers at the same clock frequency by using faster transistors in the undelayed storage circuits, while still using relatively low-frequency transistors in the delayed circuits.

 

点击下载:  PDF (1703KB)



返 回