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Techniques for fast instruction cache performance evaluation

 

作者: David B. Whalley,  

 

期刊: Software: Practice and Experience  (WILEY Available online 1993)
卷期: Volume 23, issue 1  

页码: 95-118

 

ISSN:0038-0644

 

年代: 1993

 

DOI:10.1002/spe.4380230107

 

出版商: John Wiley&Sons, Ltd.

 

关键词: Instruction cache;Cache simulation;Trace generation;Trace analysis

 

数据来源: WILEY

 

摘要:

AbstractCache performance has become a very crucial factor in the overall system performance of machines. Effective analysis of a cache design requires the evaluation of the performance of the cache for typical programs that are to be executed on the machine. Recent attempts to reduce the time required for such evaluations either result in a loss of accuracy or require an initial pass by a filter to reduce the length of the trace. This paper evaluates techniques that attempt to overcome these problems for instruction cache performance evaluation. For each technique variations with and without periodic context switches are examined. Information calculated during the compilation is used to reduce the number of references in the trace. Thus, in effect references are stripped before the initial trace is generated. These techniques are shown to significantly reduce the time required for evaluating instruction caches with no loss of accuracy.

 

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