The effects of high‐field stressing (9–10 MV/cm) with positive gate voltage on charges and defects in the SiO2layer of metal‐oxide‐semiconductor structures are reported. In Al‐gate devices negative charge builds up near the Si‐SiO2interface whereas positive charge is generated near the Al‐SiO2interface. Subsequent avalanche injection of electrons into the oxide does not annihilate the positive charge but the negative charge disappears. Similar studies were performed on polycrystalline silicon gate devices for which internal photoemission (photoI‐V) measurements are reported for the first time. In this case a negative charge distribution is observed near both SiO2interfaces after a positive stress and additional electron traps are created near the noninjecting polycrystalline silicon/SiO2interface. Similarly, a negative stress for a polycrystalline silicon gate device creates electron traps near the substrate Si‐SiO2interface, as reported previously for Al‐gate devices.