Design techniques for a 565/680 Mbit/s coder/decoder
作者:
I.C.Wood,
M.S.J.Mudd,
D.G.Taylor,
P.J.Ward,
P.H.Saul,
期刊:
IEE Proceedings I (Solid-State and Electron Devices)
(IET Available online 1985)
卷期:
Volume 132,
issue 2
页码: 68-72
年代: 1985
DOI:10.1049/ip-i-1.1985.0017
出版商: IEE
数据来源: IET
摘要:
The circuit design, process and layout techniques used to implement a high-performance silicon integrated circuit for a 565 Mbit/s multiplex and optical-fibre transmission system will be described. The IC contains 6000 transistors and operates at speeds well in excess of those normally achieved using semicustom circuit techniques, while retaining the normal advantages of semicustom design methods.
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