A three‐dimensional thermal model of generic multilevel interconnection systems in very large scale integrated (VLSI) circuits is presented. The temperature distributions are quantitatively studied using the transmission‐line matrix modeling method. The temperature increase of a triple‐level parallel and crossing interconnection‐line scheme is found to be several times higher than that of a single‐level parallel line structure if the same magnitude of current density in the 106A/cm2range is maintained. More than 50% of the temperature rise occurs across the Si substrate; the treatment of which as a perfect heat sink in many previous thermal analyses of metallization structures is, therefore, inadequate. The large thermal gradients within the SiO2insulators between different metallization levels can be eliminated and the temperature rise can be significantly reduced if the SiO2interlevel and passivation dielectrics are replaced by a material with much higher thermal conductivity. Lower temperatures would be beneficial for improving electromigration lifetime and reducing thermal stress voiding in high density VLSI multilevel interconnections.