Methodology for efficiently inserting and condensing test points
作者:
M.Youssef,
Y.Savaria,
B.Kaminska,
期刊:
IEE Proceedings E (Computers and Digital Techniques)
(IET Available online 1993)
卷期:
Volume 140,
issue 3
页码: 154-160
年代: 1993
DOI:10.1049/ip-e.1993.0022
出版商: IEE
数据来源: IET
摘要:
A technique for eliminating hard-to-test or untestable nodes in CMOS integrated circuits is presented. The technique is characterised by a speed degradation smaller than that introduced by others. Also, efficient methods for inserting and condensing test points in combinational circuits are introduced. The experimental results show that only few test points are needed to dramatically reduce the number of random patterns which are required to achieve very close to 100% fault coverage.
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