This paper reports further work on the application of systolic architectures to systems where high speed real-time feedback operations are required. In particular, transputer operated array processors which exploit the IMS/A 100 parallel processing device are used to develop flexible (general purpose) systolic realizations of adaptive/self-tuning control schemes. An important feature of this approach is the fact that the identification (and hence the controller coefficient updating) and the control signal computation phases operate asynchronously. Hence, by running the latter at a higher rate than the former, it is possible to deal effectively with cases where the system dynamics undergo ‘rapid changes’. During each updating cycle the controller is, in effect, based on a fixed control law and multiple control signals are provided.