Hybrid signed digit logarithmic number system processor
作者:
T.Stouraitis,
C.Chen,
期刊:
IEE Proceedings E (Computers and Digital Techniques)
(IET Available online 1993)
卷期:
Volume 140,
issue 4
页码: 205-210
年代: 1993
DOI:10.1049/ip-e.1993.0030
出版商: IEE
数据来源: IET
摘要:
A combination of the signed digit (SD) and the logarithmic number system (LNS) for the creation of a hybrid SD/LNS processor is investigated. Appropriate radices were chosen for the SD system by taking into account both the speed of operations and the memory storage requirements. A new technique for high-speed conversion of SD to sign-magnitude numbers was developed to enhance the overall design. The hybrid SD/LNS processor exploits the parallelism that is offered by the SD number system to boost the performance of the fast LNS processors, and compares favourably to conventional LNS processor designs.
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