My-box representation for faulty CMOS circuits
作者:
J.-E.Chen,
C.L.Lee,
W.-Z.Shen,
期刊:
IEE Proceedings G (Circuits, Devices and Systems)
(IET Available online 1990)
卷期:
Volume 137,
issue 3
页码: 225-232
年代: 1990
DOI:10.1049/ip-g-2.1990.0034
出版商: IEE
数据来源: IET
摘要:
A new logic element, My-box, is proposed to model the line faults (stuck-at-1 and stuck-at-0) and the transistor faults (stuck-on and stuck-open) of CMOS circuits, which consist of fully CMOS logic, pseudonMOS logic, dynamic CMOS logic, clocked CMOS (C2MOS) logic, CMOS domino logic and NORA CMOS logic. It can also be used to model the faults and the functions of a transmission gate logic. A procedure is described to transform a transistor level CMOS circuit to a gate-level equivalent circuit which is composed of AND, OR and the My-box logic element. A fault collapsing procedure is also derived to determine the representative set of prime faults (RSPF) for the transformed gate-level circuit. By applying this procedure to ten benchmark circuits, the number of faults can be reduced to approximately 15% of the original total faults, if the ten benchmark circuits are implemented in the fully CMOS logic.
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