AbstractA method of analyzing the effects of clock feedthrough and power supply noise on CMOS comparators is described. In addition, a new flip‐flop type comparator with large tolerance to clock feedthrough and power supply noise is developed.First, a method of analyzing clock feed‐through and power supply noise tolerance using small signal analysis of the inverter chopper comparator is described. Next, a new flip‐flop comparator whose tolerance to clock feedthrough and power supply noise is significantly greater than that of the inverter chopper comparators is proposed. Experimental results are also described. The new comparators fabricated using 1.5 μm CMOS technology show a small offset voltage (⩽ 1.5 mV) which is caused mainly by clock feedthrough imbalance. The power supply noise tolerance of these new comparators is almost twenty times larger than that of the inverter chopper com