abstractDuring the design of a VLSI system, some kind of simulation is of vital importance. Dynamic switch-level simulation is one of the most elegant techniques for evaluating the performence of the MOS circuits. This simulalOr is based on a linear switch–level model of MOS transistors, in which each transislOr is modeled as a voltage–controlled switch in series with a resislOr and an associated gate capacitance. It supports three levels of logic values–0,1 and X. Modular styles and unique data structures are utilized 10 implement the tree–walk algorithms based on charge sharing and final value computations. An easy–to–comprehend command language for the simulator is developed and provided to the user. The simulator supports both NMOS and CMOS technologies.