FRAM® Memory Products manufactured by Ramtron International Corp., which are currently in mass production use the 2T2C cell architecture. For the correct and reliable operation of this 2T2C FRAM® memory, it is very critical that the sense amplifiers are well balanced. Any imbalance in the sense amplifiers would cause a data state preference and lead to data retention or functional failures that would compromise the yield and reliability of the product. It is very possible that inherent sense amplifier imbalances will not show up till the switching in the ferroelectric capacitors has been sufficiently degraded due to extended bakes or other stress conditions. This could lead to a scenario where these inherent sense amplifier imbalance issues are not comprehended till the product is well into its production build and qualification process. In a mass production and timeline driven project this is not an acceptable situation. This paper will discuss a simple andpatentedtesting technique at wafer level that allows us to quickly characterize any data state preference issues without having to subject the wafers to long stress conditions. This paper will also discuss how this test method has been very successful in correlating imbalance and data state preference issues seen at wafer level to that seen on the final packaged product.