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Parallel architectures for RLS with directional forgetting

 

作者: L. Chisci,   E. Mosca,  

 

期刊: International Journal of Adaptive Control and Signal Processing  （WILEY Available online 1987）
卷期: Volume 1, issue 1  

页码: 69-88

 

ISSN:0890-6327

 

年代: 1987

 

DOI:10.1002/acs.4480010106

 

出版商: Wiley Subscription Services, Inc., A Wiley Company

 

关键词: Recursive least squares;Directional forgetting;Self‐tuning control;Adaptive signal processing;Parallel processing;VLSI;Systolic arrays;UD factorization

 

数据来源: WILEY

 

摘要:

AbstractEfficient parallel architectures for recursive least squares with directional forgetting are presented. Two different arrays are proposed. The first employsO(n)processors and exhibits a 1/(2n+ 3) throughput rate,nbeing the number of parameters to be estimated. The second can achieve a 1/(n+ 2) throughput rate at the expense of anO(n2)processor complexity. Both architectures make use of the UD algorithm, here properly modified so as to embody the directional‐forgetting varian

 

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