The problem of memory contention in digital scan converters (DSC) is discussed. The role of the microprocessor in DSC design is examined, and the importance of uninterrupted display in the development and use of image-processing algorithms is stressed. The drawbacks inherent in interrupt and in direct memory access are pointed out and an elegant scheme using the CPU ‘READY’ feature is suggested as an alternative, cycles during which memory contention could occur are predictable, and during these cycles the CPU is prevented from addressing the store. A specific implementation is described using the TMS9900 microprocessor in a DSC displaying sector-scanned sonar images. Timing problems are discussed in detail.