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AN EFFICIENT NETWORK ANALYSER BASED ON LINEAR ARRAY ARCHITECTURE*

 

作者: S. N METALLINOS,   D. I REISIS,   G. I STASSINOPOULOS,  

 

期刊: Parallel Algorithms and Applications  (Taylor Available online 1994)
卷期: Volume 2, issue 1-2  

页码: 139-147

 

ISSN:1063-7192

 

年代: 1994

 

DOI:10.1080/10637199408915412

 

出版商: Taylor & Francis Group

 

关键词: Linear arrays;string matching;broadband networks;network analyzer

 

数据来源: Taylor

 

摘要:

In this paper we present an array based network analyzer for Broadband Integrated Services Digital Networks. The analyzer is laid as a linear array processor. We describe the implementation of the analyzer's functions on the array processor. Apart the real-time application, the importance of this study becomes more apparent by the fact that, the resulting design can be implemented on configurable gate array and be attached to a microprocessor. Nevertheless, it is also possible to use the analyser array in combination with commercially available hardware to debug the network equipment in the development phase.

 

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