AbstractMany signal-processing problems being investigated for radar and other applications have very large computation requirements. The need for high throughput and a programmable real-time implementation for these applications can be met using parallel processing techniques. The Cluster Array Processor!CAP), a prototype parallel processor, is being developed at the MITRE Corporation specifically for signal processing applications, where the computations are frequently very regular, with the data being processed in blocks, and the control is data- independent. The performance of a parallel signal processor must be evaluated with respect to two sets of performance measures: signal processing measures and array processor measures. Array processor measures are those that apply to general-purpose processing such as bus utilization, control overhead and processing element utilization, while signal processing measures are derived from the real-time processing requirements inherent in the overall signal-processing problem.This paper presents the results of a performance evaluation of the prototype Cluster Array Processor that was accomplished using a simulation model of the parallel processor architecture. The simulation, an uninterpreted behavioral model written in VHDL, was developed in order to evaluate the processor design and to assess algorithm-to-architecture mappings. A brief description of the CAP architecture and the simulation model are followed by a discussion of the simulated performance of the CAP for a sidelobe cancellation technique that uses the Gram-Schmidt orthogonalization algorithm. Results of the simulation were verified against actual prototype performance.