The major advantage of the binary coded decimal (BCD) system is in providing rapid binary-decimal conversion. The shortcoming of the BCD system is that BCD arithmetic operations are often slow and require complex hardware. The performance of BCD operations can be improved through a redundant binary coded decimal (RBCD) representation which leads to carry-free operations. This paper introduces the VLSI design of an RBCD adder. The design consists of two small PLA's and two 4-bit binary adders for one digit of the RBCD adder. The addition delay is constant forn-digit RBCD addition (no carry propagation delay). The VLSI time and space complexities of the design as well as its layout are presented. In addition, we show that BCD to RBCD conversion can be carried out in a constant time. However, RBCD to BCD conversion requires a carry-ripple operation which can be accomplished with a complexity equivalent to that of the carry-look-ahead circuitry.