LSI fabrication process evaluation system utilizing simulators
作者:
Satoshi Tazawa,
Katsutoshi Kubota,
Kou Wada,
期刊:
Electronics and Communications in Japan (Part II: Electronics)
(WILEY Available online 1985)
卷期:
Volume 68,
issue 3
页码: 86-93
ISSN:8756-663X
年代: 1985
DOI:10.1002/ecjb.4420680310
出版商: Wiley Subscription Services, Inc., A Wiley Company
数据来源: WILEY
摘要:
AbstractWe propose a process evaluation method using channel‐doped MOS devices and process/device simulators for quantitative evaluation of contamination and surface condition. The amount of contamination is determined by comparison of the measured and simulatedC‐Vcharacteristics of an MOS capacitor. Then the MOS FET is evaluated by comparison with a theoretical idealI‐Vcharacteristic calculated from the MOS capacitor measurement data and the doping profile. The surface condition is evaluated by determining the carrier mobility from MOS FET characteristics. With these evaluation methods, we develop a new process evaluation algorithm to determine the cause of processing irregularities, whether due to contamination, damage, faulty pattern delineation, or other factors. By combining a process data base and process device simulator, we develop a process evaluation system to facilitate application of the new evaluation method. It is applied to the evaluation of MOS LSI proce
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