首页   按字顺浏览 期刊浏览 卷期浏览 Effects of fixed frequency clock offsets in synchronous digital hierarchy networks
Effects of fixed frequency clock offsets in synchronous digital hierarchy networks

 

作者: Peter E. Sholander,   Chris B. Autry,   Henry L. Owen,  

 

期刊: European Transactions on Telecommunications  (WILEY Available online 1996)
卷期: Volume 7, issue 1  

页码: 49-60

 

ISSN:1124-318X

 

年代: 1996

 

DOI:10.1002/ett.4460070106

 

出版商: Wiley Subscription Services, Inc., A Wiley Company

 

数据来源: WILEY

 

摘要:

AbstractSDH networks require synchronous clocking in order to minimize network wander and jitter. In practice, the clocks in SDH networks are not ideal and thus are not all perfectly synchronous. The operation of SDH networks with non‐ideal clocks results in undesirable wander and jitter effects. Two different philosophies are being used to minimize these undesirable synchronization effects in SDH networks. In Europe, where it is difficult to tighten clock specifications due to the multinational synchronization environment, desynchronizer designs are made more robust. In North America, where Synchronous Optical Network (SONET) is used, the specifications of both the clocks and the synchronization distribution are being tightened. Even with these different approaches, non‐ideal synchronization effects still exist in SDH networks. In particular, the STM‐N. AU, and TU overhead bytes cause gapped pointer effects when traditional fixed threshold pointer processors are used. Another type of pointer processor, a uniform pointer processor, can remove the gapped pointer effects caused by the STM‐N, AU, and TU overhead bytes. Additionally, a compensating desynchronizer may be used to remove the gapped effects caused by the VC overhead bytes. If these gapped effects are not removed. then they cause jitter and wander in a reconstructed PDH signal. This paper focuses on the case where the SDH network clocks have fixed frequency offsets. An El‐rate (2048 kbit/s) payload, which is transported over a network consisting of SDH and PDH islands, is used to show the effects of this non‐ideal clocking in SDH networks. In theory, clock frequency differences in SDH networks are accommodated by the pointer processor mechanism without slips (i.e. losing or repeating data). In practice, non‐ideal synchronization may stil

 

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