VLSI implementation of Tausworthe random number generator for parallel processing environment
作者:
J.Saarinen,
J.Tomberg,
L.Vehmanen,
K.Kaski,
期刊:
IEE Proceedings E (Computers and Digital Techniques)
(IET Available online 1991)
卷期:
Volume 138,
issue 3
页码: 138-146
年代: 1991
DOI:10.1049/ip-e.1991.0019
出版商: IEE
数据来源: IET
摘要:
A fast Tausworthe-type random number generator has been implemented as a VLSI circuit on silicon for Monte-Carlo simulation purposes in a parallel multiprocessor system environment. The generator, which has uniform distribution, has been contructed for use as a peripheral device to be connected with each processor unit. General considerations for parallel random number generation are discussed and desirable properties are reviewed as a starting point for a VLSI implementation. The hardware design is based on the maximal length shift register sequences. It involves concurrent architecture in which a single shift operation is equivalent to 16 shifts in the original shift register unit. A new 16-bit random number is generated during each shifting operation. The chip is fully microprocessor bus compatible with a 16-bit bidirectional data bus and three I/O control lines. The methods of shift register sequence segmentation are also reviewed. Practical aspects for parallel processing system purposes are given. The generator has been submitted to a comprehensive set of statistical tests.
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