The silicon‐on‐sapphire (SOS) interface has been studied using a new approach based on the use of the mechanically thinned sapphire as a metal insulator semiconductor gate insulator. A final sapphire thickness of 5 mm has been achieved. 1‐MHz capacitance‐voltage profiles exhibit a pronounced hysteresis, which is investigated using electrical and thermal stress, time‐resolved capacitance and laser‐induced photocapacitance. A native polarizable interfacial layer in SOS is shown to be the possible mechanism for the observed hysteresis. An interface model including a polarizable layer (equivalent to a reduced charge of the order of 1011e/cm2), interface states (at midgap 1×1012states/cm2/eV), and fixed charges is presented.