Comparison of two-phase latch configurations for pipelined processors in MOS VLSI: case study: a CMOS systolic multiplier
作者:
S.Summerfield,
期刊:
IEE Proceedings G (Circuits, Devices and Systems)
(IET Available online 1990)
卷期:
Volume 137,
issue 4
页码: 261-265
年代: 1990
DOI:10.1049/ip-g-2.1990.0040
出版商: IEE
数据来源: IET
摘要:
It is shown that for bit-level pipelined processors whose elements require no precharge phase, pipelining with master-slave latches gives a theoretical maximum throughput of nearly twice that of the Mead-Conway alternating phase arrangement. A comparison is made between area and power requirements as a function of clock rate, both in general terms and with reference to a design example; a pipelined multiplier implemented as a bit-level systolic array.
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