This paper describes an accurate and efficient gate‐level timing simulator that can give the waveform at each node of the circuit. Its high accuracy is attributed to a sophisticated delay model, which includes an accurate representation of the waveform, a consistent and meaningful definition of delay, a consideration of waveform slope effects at both input and output of a gate, a consideration of the multiple charging/discharging paths in the circuit, and a consideration of the various fan‐out and cell‐size effects. In order to represent the waveform accurately, the switching delay and the slope are defined and calculated carefully with the consideration of internal charges. In order to compute the waveform accurately, the effects of internal charges are investigated and a merged PN tree is used to represent a CMOS gate. Characteristics of the PN tree are described and the methods used to evaluate conducting paths are proposed. After the conducting paths are obtained, a recursive algorithm can be applied to compute the RC time constant in series‐parallel RC networks, and then the switching delay and the slope. The results, even the circuits with transmission gates are satisfactory when compared with SPICE.