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Shallow trench isolation for ultra‐large‐scale integrated devices

 

作者: K. Blumenstock,   J. Theisen,   P. Pan,   J. Dulak,   A. Ticknor,   T. Sandwick,  

 

期刊: Journal of Vacuum Science&Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena  （AIP Available online 1994）
卷期: Volume 12, issue 1  

页码: 54-58

 

ISSN:1071-1023

 

年代: 1994

 

DOI:10.1116/1.587107

 

出版商: American Vacuum Society

 

关键词: INTEGRATED CIRCUITS;FABRICATION;POLISHING;PLANAR CONFIGURATION;SILICON;SILICON OXIDES;PHOTORESISTS;THICKNESS;POLYCRYSTALS;Si;SiO2

 

数据来源: AIP

 

摘要:

A new process to form shallow trench isolation for ultra‐large‐scale integrated devices is presented. This technique utilizes chemical mechanical polish steps to provide a virtual planar surface at the end of processing for isolations of various size, ranging from 0.5 μm to several hundred μm. Superior uniformity has been obtained on wafers of 8 in. diam processed in a productionlike environment. Good device isolation also has been found.

 

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