Semiconductor microlithography is rapidly reaching a point where it becomes exceedingly difficult to shrink features at historical rates. We will no longer be able to increase process windows by going to shorter wavelengths with optical lithography, because we are running out of useable wavelengths. This necessitates either the implementation of processes with very small process windows or a transition to radically new types of lithographic technologies. Either situation presents numerous challenges to lithographers and metrologists. Particularly daunting are the requirements for gate linewidth control for microprocessors. Reducing variation requires improvement in the components of variation, each of which must be smaller than the total result. In order to improve a particular parameter, such as CD variation, metrology must be adequate for identifying improvements in the components of that parameter, not just the total. This places very tight requirements on metrology capability. Departing from optical lithography into the Brave New World of Next Generation Lithography will necessitate new metrology capabilities in several areas, not just the measurement of features on wafers. Creating the capabilities that will be needed in the future requires that funding be available for the requisite development. The need for huge amounts of funding to develop new lithographic technologies will likely necessitate a slowing down in the pace at which we shrink features. It is absolutely essential that a balance is re‐established between the prices that purchasers of chips are willing to pay and chip development and manufacturing costs. This will be very challenging with 300 mm wafer fabs coming on‐line, since low chip prices have historically been associated with overcapacity in the semiconductor industry, and it is anticipated that new lithographic technologies will be very expensive. © 2003 American Institute of Physics