A 3.5 GHz self-aligned single-clocked binary frequency divider on GaAs
作者:
M.Cathelin,
M.Gavant,
M.Rocchi,
期刊:
IEE Proceedings I (Solid-State and Electron Devices)
(IET Available online 1980)
卷期:
Volume 127,
issue 5
页码: 270-277
年代: 1980
DOI:10.1049/ip-i-1.1980.0054
出版商: IEE
数据来源: IET
摘要:
A fully planar self-aligned technology has been ultilised to fabricate a monolithic single-clocked binary frequency divider consisting of a gated master/slave flip-flop and a complementary clock-pulse generator to drive it. An optimised version of the gated m.s. flip-flop is presented along with the m. e.s.f.e.t.model used for the simulations. Correct counting from d.c. up to 5.5 GHz for the gated m.s. flip-flop and up to 3.5 GHz for the single-clocked divider are reported. The performance and evaluation of the circuits are dealt with in detail.
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