Sub-half-micron device design rules require precise control over two critical etch layers: transistor polysilicon gate definition and contact formation. The definition of the transistor polysilicon gate electrode is essential to the performance of the device. In addition, the small geometries and thin underlying gate oxide demand a high level of control over the gate dimensions. The design rules also require the formation of high-aspect-ratio contacts and vias with nearly vertical sidewalls and minimal critical dimension variation. To define these features, a deep-ultraviolet photolithography process was developed, incorporating a bottom antireflective coating (ARC). The etch processes used to translate these features into polysilicon (gates) and oxide (contacts) required anin situARC dry–develop step and a fast etch rate for high throughput with good uniformity while maintaining a high selectivity to any underlying layers. To achieve these stringent requirements, low-pressure, high-density-plasma reactors with independent substrate bias power control were needed.