With a 100 nm focus of a focusedGa+ion beam with 100 keV, we write insulating lines in electronic layers ofIn0.21Ga0.79Asquantum wells. In this way, in-plane-gate (IPG) transistors are formed which can be operated at room temperature. In a typical integration application of a common source circuit, the pull-up resistance represents a serious problem due to the high geometric aspect ratio necessary for it. For example, the typical specific sheet resistivity of theIn0.19Ga0.79Asquantum well of 1.2 kΩ needs to be increased to 100 kΩ by a 1 μm wide, about 83 μm long channel. In order to save this waste of area we introduce active loads in the form of a narrow channel. In this way, the pull-up resistor requires orders of magnitude less area and stabilizes the drain current due to velocity saturation, leading to lower supply voltages. Inverters in this technology are presented and characterized. In finite element simulations these circuits are further investigated. The operation of these systems is based on the lateral depletion of adjacent quantum well areas. The basic differences between depletion withinpnhalf spaces andpnhalf planes are discussed analytically, showing a marked dependence on dimensionality. In particular, it is shown that the ruggedness of IPGs can be explained by these phenomena.