The design and operation of a compact processor for small adaptive arrays is described. The control law is based on the minimisation of the array output power subject to a linear weight constraint. This choice enables the processor to be used in a wide range of applications using relatively simple control techniques to avoid cancellation of the wanted signal. Practical results supporting many of the design equations are provided, and several types of application are discussed. The design approach has been chosen to facilitate a future VLSI implementation.