Switch-level timing verification for CMOS circuits: a semianalytic approach
作者:
H.-G.Yang,
D.M.Holburn,
期刊:
IEE Proceedings G (Circuits, Devices and Systems)
(IET Available online 1990)
卷期:
Volume 137,
issue 6
页码: 405-412
年代: 1990
DOI:10.1049/ip-g-2.1990.0062
出版商: IEE
数据来源: IET
摘要:
The paper describes a semianalytic slope delay model for CMOS switch-level timing verification. It is characterised by classification of the effects of the input slope, internal size and load capacitance of a logic gate on delay time, and then the use of a series of carefully chosen analytic functions to estimate delay times under different circumstances. In the field of VLSI analysis, this model achieves improvements in speed and accuracy compared with conventional approaches to transistor-level and switch-level simulation.
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