Optimised bit level systolic array for convolution
作者:
J.V.McCanny,
J.G.McWhirter,
K.Wood,
期刊:
IEE Proceedings F (Communications, Radar and Signal Processing)
(IET Available online 1984)
卷期:
Volume 131,
issue 6
页码: 632-637
年代: 1984
DOI:10.1049/ip-f-1.1984.0097
出版商: IEE
数据来源: IET
摘要:
A bit level systolic array for computing the convolution operation is described. The circuit in question is highly regular and ideally suited to VLSI chip design. It is also optimised in the sense that all the cells contribute to the computation on each clock cycle. This makes the array almost four times more efficient than one which was previously described.
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