RAPAC: a high-speed image-processing system
作者:
A.C.Elphinstone,
A.P.Heron,
G.S.Hobson,
A.Houghton,
M.K.Lau,
A.R.Powell,
L.Seed,
R.C.Tozer,
期刊:
IEE Proceedings E (Computers and Digital Techniques)
(IET Available online 1987)
卷期:
Volume 134,
issue 1
页码: 39-46
年代: 1987
DOI:10.1049/ip-e.1987.0007
出版商: IEE
数据来源: IET
摘要:
The paper describes the design and operation of a real-time image processing system and outlines one of its application areas. The system consists of a dedicated hardware processor called RAPAC (a reconfigurable attached processor architecture for convolution) and a host computer which is used for algorithm development and RAPAC control. RAPAC uses hardware processor units and multiple image memories, in a software controlled architecture, to process 5 MHz streams of pixel data. This processing rate allows it to process a 256 × 256 pixel image in 20 ms, one field time of a standard TV camera. The result is either a new 256 × 256 pixel image generated from the old image or a reduced data set which describes attributes of features in the image. These attributes are used by the host computer to calculate a decision output concerning the content of the image.
点击下载:
PDF
(987KB)
返 回