Series-parallel signal generation and processing techniques are identified which may be used to circumvent the speed limitations of available logic devices in realising bit error ratio measurements for high-digit-rate transmission systems. New techniques are proposed which offer advantages in enabling devices to be used near their maximum operating rate while achieving, by virtue of the parallelism inherent in the structures proposed, yet higher data throughout rates. The specific application of these techniques to highspeed line-coded test signal generation and error detection is examined, and the series-parallel generators are shown to be particularly well suited to the economical realisation ofmB(m+1)B block-coded test signals.