Possible approaches for parallelism extraction in digital controller algorithms targeted at medium- to fine-grain parallel architectures are investigated. The methods use information on the node computation precedence of realization structures expressed in the factored state variable description (FSVD). Three architectures are considered, namely a multiprocessor system, a systolic array and PACE, a novel architecture which can support structured and non-structured algorithms within a regular processor array. It is shown that this facility makes PACE particularly promising for the implementation of controller structures expressed in terms of the FSVD.