首页   按字顺浏览 期刊浏览 卷期浏览 FOLDING TRANSFORMATIONS ON SYSTOLIC AND VLSI PROCESSOR ARRAYS
FOLDING TRANSFORMATIONS ON SYSTOLIC AND VLSI PROCESSOR ARRAYS

 

作者: M. GUSEV,   D. J. EVANS,  

 

期刊: Parallel Algorithms and Applications  （Taylor Available online 1994）
卷期: Volume 4, issue 3-4  

页码: 239-274

 

ISSN:1063-7192

 

年代: 1994

 

DOI:10.1080/10637199408915467

 

出版商: Taylor & Francis Group

 

关键词: Folding transformation;partitioned linear transformation;symmetrical mapping;interlocking translation;data dependence;algorithm transformation;double mapping;systolic array;El.l;F.2.1;B.7.1

 

数据来源: Taylor

 

摘要:

Folding transformations on processor arrays as introduced in [1] result in smaller processor arrays, more work for the processing elements, a decrease in I/O time, pipelineable implementations and circular data flow. Some implementations of folding transformations have been considered by Megson and Evans in [2], Choffrut and Culik in [3], Yaacoby and Cappello [4] and by the authors in [1, 5-7]

 

点击下载:  PDF (463KB)



返 回