A high density inductively coupled plasma (ICP) polycide etcher was studied by incorporating it into a 0.5 μm complementary metal–oxide–semiconductor process flow having a nominal 10 nm gate oxide. Polysilicon: oxide etch selectivity, sidewall profile, and critical dimension control were found to be good. Gate oxide damage was studied in detail using both antenna and large capacitor test structures in area‐ and edge‐intensive configurations. No charge buildup was detected using the antenna structures, and damage measured using large capacitors was also very low. Damage was found to be insensitive to bias power, while the sequence of extinguishing the plasma had a small effect. An experimental hardware modification significantly reduced the level of subintrinsic failures of gate edge‐intensive capacitors. Split‐lot comparisons were made of several etchers using standard hardware and processes, and the rf ICP etcher was found to result in significantly lower oxide damage than the split‐power rf triode, plasma‐mode rf diode, or microwave electron cyclotron resonance etchers studied. The lowest damage occurred in the ICP, followed by the diode. Langmuir probe measurements were made of plasma potential and ion current for the bulk etch and overetch processes used in the ICP etcher; the results are compared to wafer maps of oxide damage. Plasma potential and ion current are very uniform in this plasma, and no pattern is evident from the wafer maps of breakdown failures. The low oxide damage measured using the ICP etcher probably results from the combination of hardware and process design that ensures a uniform plasma.