A new self‐aligned subtractive gate process is proposed by alternating several masking and polycrystalline silicon gate etching steps from a conventional process to build high‐voltage (up to 100 V) and complementary thin‐film transistors (TFT) on insulating substrates. The new process is compatible with conventional TFT mask sets and standard processing techniques. The advantage of using this new process is to eliminate the difficulty in stripping photoresist on insulating substrates after high‐dose phosphorus implant and to improve the off‐state breakdown voltage in high‐voltage transistors. Complementary metal‐oxide‐semiconductor and high‐voltage TFT devices were successfully fabricated by this new process.