Extraction of interface state density profile from the maximums of the parallel conductance versus applied gate bias curvesGp(Va), using the conductance technique
作者:
C. Papadas,
P. Morfouli,
G. Ghibaudo,
G. Pananakakis,
期刊:
Review of Scientific Instruments
(AIP Available online 1992)
卷期:
Volume 63,
issue 9
页码: 4189-4191
ISSN:0034-6748
年代: 1992
DOI:10.1063/1.1143232
出版商: AIP
数据来源: AIP
摘要:
A fast method for extracting the interface trap density profile of the semiconductor‐insulator interface in metal‐insulator‐semiconductor structures is proposed. The method is based on the well known conductance technique and extracts the interface state density profile from the maximums of the parallel conductance versus applied gate bias curves,Gp(Va). In addition, this method is directly applicable to fully automated experimental setups available in industrial environments.
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