Self-testing approaches for VLSI arrays
作者:
W-K.Huang,
F.Lombardi,
期刊:
IEE Proceedings E (Computers and Digital Techniques)
(IET Available online 1993)
卷期:
Volume 140,
issue 3
页码: 175-184
年代: 1993
DOI:10.1049/ip-e.1993.0025
出版商: IEE
数据来源: IET
摘要:
A self-testing method which is applicable to 1- and 2-dimensional arrays, is presented. The method is based on a state-table-verification approach and a criterion referred to as GI (group identical) testability. GI testability is an extension and modification of PI (partition identical) testability and it is used to simplify response verification for self-testing. It is shown that the response verifier for PI testability does not always detect all faults and a new response verifier for GI-testable arrays is proposed. CGI-testable arrays which are simultaneously C and GI testable, are analysed. It is proved that a C-testable 1-dimensional array with n cells is GI testable ifn≥2T, whereTis the least common multiple of the test sequences for verifying a cell in the array. Design for testability approaches for unilateral and bilateral arrays are proposed, and similar conditions are developed for 2-dimensional arrays. Methods for reducing the size of CGI-testable unilateral and bilateral arrays are duscussed.
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