The semiconductor industry continues to fabricate integrated circuits (ICs) with faster clock speeds, increased numbers of transistors, and smaller feature sizes. A complete set of the attributes describing a new technology generation (or node) is specified by an important features size such as the12pitch of the first level of metal lines in a dynamic random access memory (DRAM). Historically, Moore’s law has been used to describe the timing associated with the three‐year cycle of new generations of memory devices. Recently, the introduction of new generations of logic devices has surpassed the three‐year node cycle of memory devices. New technology generations have another significance. Each generation requires a new set of manufacturing equipment and, recently, new materials. TheInternational Technology Roadmap for Semiconductors(ITRS) describes the technology requirements for volume manufacturing of integrated circuits (ICs) for each new technology node over the next 15 years [1]. In the 15‐year horizon of the current ITRS, industry experts are considering the possibility of a revolution in microelectronics. The ITRS predicts that the gate length of transistors at the end of the roadmap will be less than 10 nm. The ITRS also discusses the need to move beyond traditional planar CMOS during the next 15 years and the potential need to move into revolutionary technologies at the end of the roadmap. The physical properties of materials change from bulk‐like into “nano‐like.” For example, on‐chip interconnects will have dimensions that have nanowire properties. The development and manufacture of new generations of ICs or their successors will require new measurement technology. There will be many different challenges for metrology over the next 15 years. This paper describes these challenges. © 2003 American Institute of Physics