Line coding is shown to provide an effective means of controlling modulation jitter associated with digital pulse-position modulation (PPM), enabling simple phase-locked-loop (PLL) timing extraction circuits to be employed. The combination of a specific 9B2-32 code and a suitably designed third-order PLL with a maximally flat response is proposed and studied for the purpose of obtaining at dependent regenerators both frame and slot synchronisation signals. Jitter accumulation along a chain of such synchronisers is considered and shown to be acceptable, establishing that the combination of 9B2-32 line code and PLL synchroniser is well suited to repeatered digital PPM transmission.