A study of severalSi0.8Ge0.2p-channel heterostructures with self-aligned poly-Si metal–oxide–semiconductor gates were carried out. A novel fabrication process was developed which is compatible with the strained Si/SiGe system, and it has allowed Hall and resistivity measurements to be performed at room temperature and at 4.2 K. The structures were numerically modelled to calculate the charge distribution with temperature and with gate voltage and the results have shown good agreement with experiment. Hall measurements at 4.2 K have shown consistent SiGe channel Hall mobility enhancements of×3over theSiO2/Sichannels in the same devices. Room temperature effective mobilities were measured for a buriedSi0.8Ge0.2p-channel metal–oxide–semiconductor field-effect transistor heterostructure using capacitance–voltage measurements to calculate the carrier density. Mobilities are consistently over300 cm2/V sand the low temperature studies, together with measurements of comparable modulation doped heterostructures, and secondary-ion-mass spectroscopy depth profiles suggest that this mobility is at present limited by the quality and proximity of theSiO2/Siinterface. ©1997 American Institute of Physics.