Hot carrier induced interface trap annealing in silicon field effect transistors
作者:
N. C. Das,
V. Nathan,
期刊:
Journal of Applied Physics
(AIP Available online 1993)
卷期:
Volume 74,
issue 12
页码: 7596-7599
ISSN:0021-8979
年代: 1993
DOI:10.1063/1.354987
出版商: AIP
数据来源: AIP
摘要:
Interface traps are created in metal‐oxide‐semiconductor field‐effect transistors when hot carrier stressing is done with the maximum substrate current biasing condition (Vd=6.0 V andVg=2.9 V). Unlike trapped oxide charge, the interface traps are not annealed by keeping the device at room temperature for 24 h. However, by applying reverse bias with high positive drain voltageVdand negative gate voltageVg, the hot carrier induced interface traps can be completely annealed out. This is confirmed by both transconductance and charge pumping measurements. There is a direct relationship between the substrate current and annealing of interface states by reverse stressing. The possible mechanism of interface state annealing is discussed.
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