Formation of Si–SiO2stacked‐gate heterostructures requires (i) preparation of Si surfaces prior to interface formation and oxide deposition, (ii) oxide deposition, (iii) polysilicon gate electrode deposition, and generally (iv) post‐deposition doping of the gate electrode. Mid‐ and/or end‐process rapid thermal annealing performed in inert or oxidizing ambients may also be necessary to optimize device performance.Fourphasesin the development of an integrated processing protocol for stacked‐gate structures are described in which these steps have been modified, and continuously improved. Process tools have evolved from (i)single‐functionchambers for (a) surface cleaning/passivation, and (b) thin film deposition, to (ii)dual‐function/singleprocessplasma chambers for (a)in‐situsurface cleaning and interface formation and (b) oxide deposition, and finally to (iii)multi‐function/dualprocesschambers in which all of the above process steps are doneinsitu, but by more than one processing technique. This last approach has culminated in chambers which can accommodate (i)low‐temperatureplasma‐assisted interface formation at ∼300 °C, (ii)intermediate‐temperaturerapid thermal dielectric and polysilicon depositions at 600–800 °C, and (iii)higher‐temperaturerapid thermal annealing at 900–1000 °C.