Evaluation and control of device damage in high density plasma etching
作者:
P. K. Gadgil,
T. D. Mantei,
X. C. Mu,
期刊:
Journal of Vacuum Science&Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena
(AIP Available online 1994)
卷期:
Volume 12,
issue 1
页码: 102-111
ISSN:1071-1023
年代: 1994
DOI:10.1116/1.587165
出版商: American Vacuum Society
关键词: MOS JUNCTIONS;SEMICONDUCTOR DEVICES;DAMAGE;EVALUATION;CONTROL;SILICON;POLYCRYSTALS;ETCHING;MAGNETOPLASMA;DENSITY;Si;SiO2
数据来源: AIP
摘要:
The effects of polysilicon etch plasma conditions on metal–oxide–semiconductor (MOS) capacitor breakdown andn‐channel MOS transistor (NMOS) performance have been investigated. A high density electron cyclotron resonance (ECR) plasma source with multipolar magnetic confinement was integrated into a full NMOS process flow. The polysilicon etch plasma process parameters for designed experiments were microwave power, overetch time, rf bias, and plasma radial uniformity. MOS capacitor leakage currents increase with longer polysilicon edge lengths on gate oxide, higher ion density, and higher ion energy during the polysilicon overetch step. Lower NMOS transistor transconductance and higher threshold voltages correlate with longer overetch times and high microwave power and rf bias during the overetch step. Device performance degradation increases with decreasing channel length, and the exposure of the source and drain oxide edges to a high density flux is thought to be the main cause for observed degradation. A high rate, selective, and low damage polysilicon etch process can be obtained using a high density (≳1011cm−3) and moderate ion energy (<30 eV) ECR discharge, with moderate power and zero applied rf bias during the overetch step.
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