A parallel arithmetic unit using a saturated-transistor fast-carry circuit
作者:
T.Kilburn,
D.B.G.Edwards,
D.Aspinall,
期刊:
Proceedings of the IEE - Part B: Electronic and Communication Engineering
(IET Available online 1960)
卷期:
Volume 107,
issue 36
页码: 573-584
年代: 1960
DOI:10.1049/pi-b-2.1960.0171
出版商: IEE
数据来源: IET
摘要:
The paper describes a transistor switch technique which is of particular importance in applications where a large number of switches have to be connected in series and where the propagation time of information through these switches has to be a minimum. It is thus of importance in parallel addition, and its use in this connection has been successfully demonstrated, yielding an addition time over 24 digits of 200 millimicrosec. The technique is reasonably economical, and the paper also shows how it can be used in conjunction with more conventional logical circuits to provide a simple arithmetic unit.
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