Achieving efficiency in parallel sparse sub-matrix Cholesky factorization is known to be difficult. The relevance of the underlying architecture in obtaining good performance is demonstrated, by choosing the linear array. The linear array architecture is chosen to suit the data flow pattern inherent to sub-matrix Cholesky scheme. The linear array is synthesized on the reconfigurable transputer based PARAM (and the MEIKO CSN) machine. The data structure used is an array of linked lists. Results obtained indicate almost linear speed-up up to 64 processors though the tests were conducted for 128 processors This highlights the significance of the underlying architecture for an efficient parallel implementation.