A simple capless annealing process for post‐implantation annealing of InP material is described. The technique incorporates a simple boat design and uses InP+Sn as the source of phosphorus overpressure. Using this process, Si‐implanted (4×1012cm−2dose) InP layers show mobilities at room temperature and 77 K in the range of 3200 and ∼10 000 cm2/Vs, respectively. Dopant depth profiles with peak donor densities of 2×1017cm−3and minimal redistribution of impurities were obtained. Depletion‐mode InP metal‐insulator‐semiconductor field‐effect transistors fabricated with 4‐&mgr;m gate lengths using ion‐implanted channel and source‐drain regions, show channel mobilities of 2500 cm2/Vs.