A BIST ram architecture with parallel testing in a microprogram rom
作者:
Jung‐Meng Huang,
Feipei Lai,
期刊:
Journal of the Chinese Institute of Engineers
(Taylor Available online 1993)
卷期:
Volume 16,
issue 5
页码: 685-690
ISSN:0253-3839
年代: 1993
DOI:10.1080/02533839.1993.9677542
出版商: Taylor & Francis Group
关键词: BIST;RAM;ROM;parallel testing
数据来源: Taylor
摘要:
Symmetrically simple test patterns for parallel testing of row/column pattern‐sensitive faults in RAMs are proposed in this paper. Based on the concept of the maximum leakage current among the RAM cells, the worst case testing becomes the critically efficient method for RAM testing. Due to the simplicity of generating test patterns, we can implement a BIST RAM with test procedures stored in a microprogram ROM to reduce the cost and time of testing. The test complexity of row/column pattern‐sensitive faults is reduced toO(N) in anNbits RAM as compared withO(N3/2) of [1].
点击下载:
PDF (468KB)
返 回