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Processing and performance of integrated ferroelectric and CMOS test structures for memory applications

 

作者: G.J. M. Dormans,   P.K. Larsen,   G.A.C.M. Spierings,   J. Dikken,   M.J. E. Ulenaers,   R. Cuppens,   D.J. Taylor,   R.D. J. Verhaar,  

 

期刊: Integrated Ferroelectrics  (Taylor Available online 1995)
卷期: Volume 6, issue 1-4  

页码: 93-109

 

ISSN:1058-4587

 

年代: 1995

 

DOI:10.1080/10584589508019356

 

出版商: Taylor & Francis Group

 

数据来源: Taylor

 

摘要:

The feasibility of integrating ferroelectric thin films with silicon CMOS technology was investigated by processing a ferroelectric process evaluation module which contains ferroelectric and CMOS test structures and some memory cells. The smallest cells have a ferroelectric capacitor (FECAP) of 25 μm2. The FECAPs were made with Pt/Ti electrodes and with Pb(Zr,Ti)O3deposited by a modified sol-gel technique or by organometallic chemical vapour deposition. The back-end processing includes the insulation and interconnection of the FECAPs and the MOS transistors. The ferroelectric processing has only a slight influence on the CMOS properties. The properties of the FECAPs improve significantly by an additional anneal in oxygen. Both CMOS and FECAP properties allow a proper functioning of the memory cells. These can be reliably operated at supply voltages as low as 3 V and pulse widths down to 20 ns. The endurance of the memory cells exceeds 1013read/write cycles.

 

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